Elementary cell of a linear filter for image processing

ABSTRACT

The present invention relates to an elementary cell of a linear filter for image processing, as well as to a corresponding module, element and process. The cell comprises a data circulation output and a calculation output, as well as a main delay line and an auxiliary delay line in parallel. Delay line selection means (MUX 4 ) make it possible to link the input of the cell to the circulation output by way of one or other of the delay lines. The cell also comprises an adder having two inputs which can be linked respectively to the input of the cell and to the output of the main delay line, by calculation selection means (MUX 1 , MUX 2 ) and a multiplier at the output of the adder, connected to a multiplier coefficients memory. Application to linear filtering for image processing and to random access for motion compensation.

This application claims the benefit under 35 U.S.C. §365 ofInternational Application PCT/EP01/03523, filed Mar. 29, 2001, whichclaims the benefit of French Application 0007851, filed Jun. 20, 2000and which claims the benefit of European Application No. 00400991.6,filed Apr. 10, 2000.

The present invention concerns an elementary cell of a linear filter forimage processing, as well as an associated module, element and process.

BACKGROUND OF THE INVENTION

Systolic architecture structures are known which make it possible toperform linear spatial filtering in a modular and flexible manner. Suchstructures comprise elementary cells in cascade. Each of them isprovided with a register making it possible to impose a delay of apoint, a memory capable of storing multiplier coefficients, a multiplierfor performing multiplications by these coefficients of the datareceived and an adder intended for sequentially adding the productsobtained to the sum of the products originating from the downstreamcells.

Such embodiments will be found in the article “Real-Time Systolic ArrayProcessor for 2-D Spatial Filtering”, by Aboulnasr and Steenaart, IEEETransactions on Circuits and Systems, Vol. 35, No. 4, Apr. 1988, pp.451–455 and in the article “High-Speed Architectures for Two-DimensionalState-Space Recursive Filtering”, by Zhang and Steenaart, IEEETransactions on Circuits and Systems, Vol. 37, No. 6, Jun. 1990, pp.831–836.

BRIEF SUMMARY OF THE INVENTION

The subject of the present invention is an elementary cell based on anovel linear filter architecture, which allows a reduction in the numberof cells required and an appreciable improvement in the processingefficiency, in particular in terms of consumption, in the presence ofhorizontal and/or vertical symmetries in the filtering coefficients.

The present invention also relates to a cell of this kind which permitsimage expansions and compressions while offering the above advantages,in particular within the framework of multiphase interpolation.

The cell of the invention can also be adapted to random access, inparticular for interpolation with motion compensation.

The invention furthermore relates to a linear filtering module based onsuch cells, as well as to a linear filtering element relying on thecooperation of several modules.

The element of the invention can allow the implementation of horizontaland/or vertical spatio-temporal filtering with increased efficiency.

The subject of the invention is moreover a linear filtering processhaving the abovementioned advantages.

Accordingly, the invention relates to an elementary cell of a linearfilter for image processing, comprising:

-   -   an input, intended to sequentially receive data relating to        pixels of an image to be processed,    -   a circulation output, intended to sequentially transmit these        data with a delay,    -   a calculation output, intended to sequentially transmit results        obtained by a processing of these data in the said cell,    -   a main delay line having an input capable of being linked to the        input of the cell and an output capable of being linked to the        circulation output and to the calculation output of the cell,    -   a coefficients memory, provided so as to contain at least one        multiplier coefficient, and    -   a multiplier connected to the coefficients memory, having an        input and an output which are capable of being linked        respectively to the output of the delay line and to the        calculation output of the cell, this multiplier being intended        to perform multiplications on the data received at the input of        the multiplier by at least one of the multiplier coefficients of        the coefficients memory and to transmit via the output of the        multiplier the result obtained.

According to the invention, the main delay line is capable of producinga maximum shift corresponding to at least two pixels of the image to beprocessed and in that the cell also comprises:

-   -   an auxiliary delay line having an input and an output which are        capable of being linked respectively to the input of the cell        and to the circulation output of the cell,    -   an adder having a first and a second input which are capable of        being linked respectively to the input of the cell and to the        output of the main delay line, and an output capable of being        linked to the multiplier,    -   delay line selection means having a first and a second state,        these means being intended to link the input of the cell to the        circulation output of the cell by way of the main delay line in        the first state and by way of the auxiliary delay line in the        second state,    -   and calculation selection means having at least two states,        these means being intended to link the input of the cell and/or        the output of the main delay line to the corresponding inputs of        the adder, in these states respectively.

The expression “delay line” should be understood to mean any systemwhich can impose a delay of one or more pixels in the sequential datastream, including a register.

Thus, the cell of the invention differs in particular from those of thestate of the art through the presence of a main delay line which makesit possible to impose delays greater than a pixel. Unlike the existingcells, it permits horizontal and/or vertical symmetries to be taken intoaccount by virtue of the possible use of two delay lines in parallel andof the presence of an adder which can form the sum of the data at theinput and at the output of the main delay line. This cell thereforemakes it possible to impose a delay corresponding to the relevantsymmetry, in the main delay line, whilst imposing another delaycorresponding to the transmission of the data downstream of the cell(for example of a pixel or of a line) in the auxiliary delay line.

It should be noted that with the improvement of efficiencies in thefabrication of dynamic RAM memories and the appearance of more precisetechnologies, it is possible to include same in the elements insignificant quantities for line memories, and in more limited quantitiesfor frame memories. Such RAMs are advantageously used for the main delaylines, and possibly auxiliary delay lines, of the cells of theinvention. These cells thus allow a flexible architecture, making itpossible to access a multitude of spatio-temporal filter structuresconventionally encountered in video processing applications, simply byreconfiguring the interconnections between operators employed.

The cell of the invention makes it possible to build a reconfigurablenetwork making it possible to satisfy, by simple parameterization,applications including spatio-temporal filtering or frame interpolationwith motion compensation.

According to a preferred implementation, the cell of the invention isadopted for a single-development ASIC circuit which can target aconsiderable number of applications which call upon filtering.

According to another preferred implementation, the cell of the inventionis utilized in a VLSI circuit, which has the advantage of being moreoptimized as regards area of silicon. One particular structure is thenadvantageously selected from the possible structures, so as to defineone and only one interconnection configuration satisfying a singletargeted application.

In both these implementations, the cell network obtained and theassociated interconnection system, by dint of their regularity, lead tothe simplicity of the placement/routing which relies on repetition ofidentical blocks. Moreover, the number of cells used can be altered, andmay be reduced or increased.

According to yet another advantageous implementation, the cell of theinvention is used in an FPGA circuit (Field Programmable Gate Array).

The cell of the invention has the advantage of being able to fulfilspatio-temporal filtering and random access functions. It thereforecaters particularly well for the requirements of frame interpolationencountered in the conversion of video standards, frame timingconversion (upconversion for television or PC) and image formatconversion (for example from the TV format to the HD TV format).

Filtering in the vertical or horizontal axis of the image or the timeaxis of a sequence, involved in these applications, requires the use ofline memories and/or frame memories whose number and management arepreferably optimized. The architecture relying on the cell of thepresent invention permits this optimization, thereby avoiding any novelinvestigation from the conceptual standpoint.

Preferably, at least one of the delay lines comprises at least onedynamic RAM.

Advantageously, the second input of the adder is capable of being linkednot only to the output of the main delay line, but also to the output ofthe auxiliary delay line. The calculation selection means then make thecorresponding connection possible.

In a first advantageous embodiment of the delay lines, the main andauxiliary delay lines are respectively capable of producing maximumshifts of at least one line and one point, the auxiliary delay linepreferably comprising a register.

This embodiment is adapted for taking into account horizontalsymmetries. It has the advantage of employing just a simple register forthe auxiliary delay line. By way of example, the shifting capacity ofthe main delay line is ten lines.

According to a second advantageous embodiment of the delay lines, themain and auxiliary delay lines are respectively capable of producingmaximum shifts of at least two lines and at least one line.

This embodiment, for its part, is adapted for taking into account bothhorizontal and vertical symmetries, but it requires the use of two lineswith adequate FIFO memories (which may in particular comprise RAMs). Inthe presence of purely vertical symmetries (pure vertical filter,rectangular filter with no horizontal symmetries), the filter obtainedfrom such cells offers savings in consumption. By way of example, theshifting capacities of the main and auxiliary delay lines are ten linesand one line respectively.

In the presence of both horizontal and vertical symmetries, thehorizontal symmetries are preferably favoured by the employing of thefirst embodiment. This choice is in fact economical. However, employingthe second embodiment may still be advantageous in the presence ofvertical symmetries with no conflict with horizontal symmetries (crossfilter, central column of a rectangular filter also having horizontalsymmetries).

The data relating to each pixel correspond to the components consideredfor this pixel. Thus, a pixel can in particular be associated with asingle component, of luminance or of chrominance, by the use of one word(of 10 bits for example). It can also be associated with threecomponents (one luminance component and two chrominance components),through the use of three words.

Advantageously, the coefficients memory consists of a memory intendedfor storing a bank of coefficients and the cell comprises means forselecting one of these coefficients.

Thus, the coefficients may be downloaded just once during initializationof the system, and be selected for each of the cells at the moment offiltering.

In a preferred embodiment, the cell comprises shift disabling means forat least one of the delay lines.

These disabling means permit image expansion, by temporal freezings ofthe data circulating in the cells, possibly corresponding to pointdisablings and/or line disablings.

The calculation selection means advantageously comprise:

-   -   a first multiplexer having a first input linked to the input of        the cell, a second input linked to the zero and an output linked        to the first input of the adder corresponding to the input of        the cell, and    -   a second multiplexer having a first input linked to the output        of the main delay line, a second input linked to the zero and an        output linked to the second input of the adder corresponding to        the output of the main delay line.

Moreover, the cell preferably comprises at least one control lineintended for downloading control information to at least one item of thecell, the control lines being chosen from:

-   -   at least one line for addressing multiplier coefficients        intended for the coefficients memory,    -   at least one line for addressing parameters for selecting        coefficients, intended for the coefficients memory, these        parameters preferably consisting of address bits,    -   at least one line for addressing data for activating and for        deactivating the shift disabling means, these data preferably        comprising information on the linewise and pointwise shift        disabling,    -   at least one line for addressing delay selection parameters,        intended for at least one of the delay lines,    -   at least one line for addressing state selection parameters,        intended for the delay line selection means and/or calculation        selection means, these parameters preferably consisting of state        control bits,    -   and any combination of these addressing lines.

The delay line selection and/or calculation selection meansadvantageously comprise switches, such as multiplexers, that is to sayitems having steering functions.

Moreover, the subject of the invention is a module of a linear filterfor image processing, comprising at least two cells in accordance withthe invention. These cells are arranged in cascade in the module andconsist of an input cell, intermediate cells and an output cell. Themodule also comprises addition means linked to the calculation outputsof the cells and having an input linked to the input of the input cell,a circulation output linked to the circulation output of the output celland a calculation output downstream of the addition means.

Advantageously, the cells are identical and/or four in number.

Preferably, for the sum of results originating from more than two cells,the addition means comprise adders each having two inputs and oneoutput, which are arranged in series in several strata, in a pyramidalmanner.

According to an advantageous embodiment, the module comprises randomaccess selection means, in particular for motion compensation, having afirst and a second state. These means are intended to connect the inputof each of the cells to the first input of the adder of this cell in thefirst state, and the output of at least one of the delay lines of eachof the cells to the first input of the adder of one of these cells inthe second state.

This embodiment can be used in particular for motion-compensatedinterpolation. By cascading several cells according to the invention, asliding window is in fact created in which it is possible to accesspixels at any, nonsequential position.

In an advantageous form of this embodiment with random access, the maindelay line of each module is associated with a dual port RAM, whichmakes it possible to increase the access capacities. In anotheradvantageous embodiment, employing line memories of sufficient capacity,these delay lines themselves serve to obtain the desired accesses. In avariant embodiment, the auxiliary delay lines are also used for randomaccess, preferably in parallel with the main delay lines.

The disposition of the line memories for random access is flexible andmakes it possible to vary the dimension of the access window as afunction of requirements, for example of the amplitude of the motionvectors in a motion-compensated filter. Moreover, according to anadvantageous embodiment, the line memories and optionally the associatedRAMs are provided so as to permit splitting over two adjacent videoframes, this allowing simultaneous access to both these frames.

The invention also relates to a linear filtering element for imageprocessing, comprising at least two modules in accordance with theinvention, this element also comprising addition means linked to thecalculation outputs of at least two of the modules.

It is thus seen that the element of the invention can exhibit thefollowing various advantages, separately or in combination according tothe embodiments concerned:

-   -   offer a multi-purpose and flexible architecture making it        possible to access a multitude of spatio-temporal filter        structures and interpolators with motion compensation by simple        software reprogramming of certain parameters,    -   be the basis of an architecture using a limited number of types        of different items thus reducing the development time,    -   permit an architecture using an optimized number of        inputs/outputs, this representing a heavy constraint when an        element is targeted,    -   allow regularity of the architecture leading to fast        placement/routing, due in particular to the repetitive basic        modules.

Advantageously, the modules are arranged in cascade and the element alsocomprises input selection means having a first and a second state,arranged between at least one of the modules, the so-called upstreammodule, and the consecutive module the so-called downstream module.These input selection means are intended to link the input of theupstream module to the circulation output of the downstream module inthe first state, and to an additional input line in the second state.

This embodiment is a flexible way of permitting the employing ofspatio-temporal filterings. Specifically, by placing modules in seriesit is possible to circulate a video signal in succession through thesemodules for spatial filtering, whilst by placing modules in parallel itis possible to introduce several video signals associated with variousinstants and thus to permit temporal filtering.

Advantageously, the modules of the element are identical and/or four innumber.

Preferably, for the sum of results originating from more than twomodules, the addition means comprise adders each having two inputs andone output, arranged in series in several strata, in a pyramidal manner.

The invention also applies to a linear filtering process for imageprocessing, in which:

-   -   data relating to pixels of an image to be processed are sent        sequentially to inputs of elementary cells in casoade, while        respectively imposing, in these cells, transmission delays for        these data,    -   multiplications by multiplier coefficients are performed in at        least one part of these cells on the data received by these        cells, so as to obtain products, and these products are added        together.

According to the invention, in at least one of the cells:

-   -   a main delay and an auxiliary delay less than the main delay are        imposed on the data received by the cell, by means of two delay        lines, respectively main and auxiliary, in parallel,    -   the data received by the cell are added together, upstream and        downstream of the main delay line so as to obtain sums and the        multiplications are performed on these sums, and    -   the data received by this cell are transmitted downstream of the        cell, with the auxiliary delay.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood and illustrated by means of thefollowing exemplary embodiments and implementations, which are in no waylimiting, with reference to the appended drawings in which:

FIG. 1 represents a particular embodiment of an elementary cell inaccordance with the invention;

FIG. 2 shows a basic module formed from four cells such as that of FIG.1;

FIG. 3 shows a final network employed in an element, formed from fourmodules such as that of FIG. 2;

FIG. 4 represents complementary implementational items for formattingand for multiplexing of the element of FIG. 3;

FIG. 5 shows diagrammatically in schematic form a first exemplaryconfiguration of the element of FIG. 4, for a horizontal and verticalfilter with horizontal symmetry;

FIG. 6 diagrammatically shows in schematic form a second exemplaryconfiguration of the element of FIG. 4, for a temporal vertical filter;

FIG. 7 diagrammatically shows in schematic form a third exemplaryconfiguration of the element of FIG. 4, for a horizontal filter with oddsymmetry;

FIG. 8 shows a configuration of the element of FIG. 4 for a horizontaland vertical expansion;

FIG. 9 shows a configuration of the element of FIG. 4 for a horizontaland vertical compression (undersampling);

FIG. 10 illustrates a bilinear interpolation in a frame T from twoframes T1 and T2 flanking it,

FIG. 11 represents a basic module supplemented with respect to that ofFIG. 2, so as to permit random access for motion compensation;

FIG. 12 is a block diagram showing the address generation device used inan element for random access based on four modules such as that of FIG.11;

FIG. 13 illustrates the items for pixel access without interpolation inan element for random access based on four modules such as that of FIG.11;

FIG. 14 diagrammatically shows in schematic form a first exemplaryconfiguration of the element of FIGS. 12 and 13, for random access to asingle video input (random access on 32 lines);

FIG. 15 diagrammatically shows in schematic form a second exemplaryconfiguration of the element of FIGS. 12 and 13, for random access totwo video inputs (dual random access on 16 lines); and

FIG. 16 diagrammatically shows in schematic form a third exemplaryconfiguration of the element of FIGS. 12 and 13, for random access tofour pixels without interpolation.

The content of these figures should be regarded not only asillustrative, but also as complementary to the description.

DETAILED DESCRIPTION OF THE INVENTION

In the figures, identical or similar items are denoted by the samereferences.

The schematic representations of FIGS. 5 to 7 and 14 to 16 show only theitems required for the understanding of the examples. They are obtainedby constructing various filters through appropriate configurations ofthe multiplexers of the system. Thus, in particular, theserepresentations do not take account of the fact that each multiplier isassociated with a bank of coefficients and the shifting and roundingoperations on the results are not represented.

The present description comprises a first part developing embodimentscentred around linear filtering (with reference to FIGS. 1 to 9), and asecond part devoted to random access for motion compensation (withreference to FIGS. 10 to 16). The embodiments of the second part arederived from those of the first part, by adding specific items tocertain blocks.

Throughout what ensues, a “module” denotes a functional entity based onan assemblage of elementary cells, and a “network”, a functional entitybased on an assemblage of modules (hence of cells) and which is thebasis of an element. In the examples described, the cells of a networkare all identical, and interconnected with one another by multiplexersand adders.

Moreover, the terms “pixel” or “point” are understood hereinafter forsimplicity to mean the data relating to a pixel, which are transmittedby a video line.

The exemplary architectures which follow employ 16 basic cells, thepixels being represented by 10-bit words. In variant embodiments, thenumber of elementary cells is higher and/or the word widths aredifferent.

According to an advantageous embodiment, several networks are cascaded,the implementation of a network being limited for example to sixteencells. This embodiment is applicable to the two functionalities oflinear filtering and random access. It makes it possible to solve theproblems of limiting the footprint or area of each element, whilstmaking it possible to obtain wider filters in linear filtering mode, andlarger vector amplitudes in random access mode.

An elementary cell 1 (also referred to as a basic cell) in accordancewith the invention (FIG. 1) has an input 2 for a video signal (IN_VIDEOline), an output 3 for a video signal after delay (OUT_VIDEO line) andan output 4 for a calculation result (OUT_CALC line). It comprises:

-   -   one delay line (LAR) 5 which can be disabled (by a WE_LINE        control line 12, with WE standing for Write Enable) whose        capacity ranges from 1 point to 2055 points on 10 bits,    -   one register 16 which can be disabled (by a WE_POINT control        line 13) in parallel with the LAR 5, which forms an auxiliary        delay line 6,    -   one adder 7 with two 10-bit inputs 21 and 22 and one 11-bit        output 23,    -   two 10-bit registers 31 and 32 at the head end of the adder 7        (inputs 21 and 22 respectively),    -   one 11-bit register 33 at the output 23 of the adder 7,    -   one multiplexer MUX4 for generating (output 53) the signal at        the output 3 of the cell 1, from the register 16 (input 51) or        from the LAR 5 (input 52),    -   one multiplexer MUX3 for generating (output 49) a video        emanating from the LAR 5 (input 47) or from the register 16        (input 48),    -   one multiplexer MUX5 making it possible to select at the output        56 the input signal (input 54) or a return for random access        (input 55),    -   two multiplexers MUX1 and MUX2, MUX1 having a first input 41        linked to the output 56 of MUX5, a second input 42 at 0 and an        output 43 linked to the adder 7 and MUX2 having a first input 44        linked to the output 49 of MUX3, a second input 45 at 0 and an        output 46 linked to the adder 7, making it possible to force the        videos to 0 at the inputs 21 and 22 of the adder 7,    -   one multiplier 8 of 11 bits (input 24) by 12 bits (input 25)        with output 26 of 23 bits to the output 4 of the cell 1,    -   one RAM bank 9 of 64 12-bit coefficients linked to the input 25        of the multiplier 8 and addressable by a 6-bit ADR_COEF        addressing line 19, this bank 9 comprising a 64×12 dual port        RAM,    -   one 12-bit register at the output of the bank 9 of coefficients        and    -   one 23-bit register 34 at the output of the multiplier 8.

The delay line 5 is obtained through the association 15 of two 512×20single-port RAMs. This association 15 operates (in respect of linearfiltering) as a single block whose delay lies between 1 and 2048 clockcycles and is supplemented with registers and multiplexers (which leadto a delay of 2055 points). In other embodiments, it is replaced by anyother line memory organized as a FIFO, whose depth is programmable.

This basic cell 1 effects the product between a video pixel and one ofthe coefficients emanating from the bank 9. The multiplexers MUX1 andMUX2 define the video input, or the added video inputs, of themultiplier 8. The multiplexer MUX4 defines the video used on the nextcell, the multiplexer MUX3 directs the video used on the input 22 of theadder 7 and the multiplexer MUX5 directs the video used on the input 21of the adder 7. The five multiplexing bits, the delay value programmedin the LAR 5 and the coefficients contained in the bank 9 are all neededto configure this cell 1.

The cell 1 is configured in particular at the level of the five 10-bitmultiplexers MUX1, MUX2, MUX3, MUX4 and MUX5. Five positioning bits aretherefore necessary, distributed over a single byte. The coefficientsalso form part of the configuration: they are downloaded during aninitialization phase, just like the positioning bits for themultiplexers, and remain the same throughout the operating phasecorresponding to this configuration.

During the operating phase, a certain number of check bits aredynamically switchable at the pixel rate. This is the case for:

-   -   addressing bits (line 19) of the bank 9 of coefficients: make it        possible to assign the coefficient which is appropriate to        within a pixel,    -   bits WE_LG (line 12) and WE_PT (line 13): make it possible to        disable the linewise and pointwise shifting of the video,        required in particular in filters for expanding image format in        the vertical and/or horizontal direction.

The basic cell 1 disclosed is multi-purpose and flexible: it makes itpossible to construct filters of variable configuration according to thehorizontal and vertical dimensions of the image, or according to thetemporal dimension.

The interconnecting of the basic cells relies on three steps: formationof modules each grouping together four basic cells, association of themodules in a final network and selection and formatting of the signalsintended to be directed to the output of the network.

Each module 60 (FIG. 2) comprises:

-   -   four basic cells 61, 71, 81 and 91 in series (respectively        having inputs 62, 72, 82 and 92, circulation outputs 63, 73, 83        and 93 and calculation outputs 64, 74, 84 and 94),    -   two adders 101 and 102 having 23-bit inputs 102 and 103 (adder        101) and 106 and 107 (adder 105) respectively linked to the        calculation outputs 64, 74, 84 and 94 of the cells 61, 71, 81        and 91 and 24-bit outputs 104 (adder 101) and 108 (adder 105)        and    -   one adder 110 having 24-bit inputs 111 and 112 respectively        linked to the outputs 104 and 108 of the adders 101 and 105 and        a 25-bit output 113.

The sum of the added results from four multipliers 68, 78, 88 and 98respectively of the cells 61, 71, 81 and 91 is obtained at the output114 (calculation output coming from the calculation output 113 of theadder 110) of this module 60. The input video delayed by the sum of thedelays produced in each of the cells of the module 60 is also available(circulation output 93).

This module 60 of four cells is designed so as to be furnished with justone video input 62, but it can be configured either in vertical orhorizontal mode.

A final network 120 (FIG. 3) is furnished with four modules 130, 140,150 and 160 of four basic cells each. The association of these modulescan make it possible to obtain a filter with 16 coefficients, but it isalso possible to employ the four results from the four modulesseparately or else two results originating from the sum of two modules.

The network 120 of the example illustrated comprises:

-   -   four cascaded filter modules 130, 140, 150 and 160, respectively        having inputs 132, 142, 152 and 162, direct video outputs        (circulation outputs) 133, 143, 153 and 163 and calculation        outputs 134, 144, 154 and 164,    -   four 10-bit registers 138, 148, 158 and 168 respectively at the        circulation outputs 133, 143, 153 and 163 (outputs to OUT_VIDEO1        . . . 4 lines),    -   four 25-bit registers 139, 149, 159 and 169 respectively at the        calculation outputs 134, 144, 154 and 164 163 (outputs to        OUT_CALC1 . . . 4 lines),    -   three multiplexers 141, 151 and 161 respectively associated with        the three modules 140, 150 and 160, each respectively having an        output 147, 157 and 167 linked to the input 142, 152 and 162 of        the corresponding module, a first 10-bit input 145, 155 and 165        linked to the circulation output 133, 143 and 153 of the        upstream module 130, 140 and 150 and a second 10-bit input 146,        156 and 166 for video input lines IN_VIDEO2, IN_VIDEO3 and        IN_VIDEO4,    -   two 25-bit adders 170 and 175 adding pairwise the calculation        results from the modules 130 and 140 on the one hand (inputs 171        and 172 of the adder 170) and from the modules 150 and 160 on        the other hand (inputs 176 and 177 of the adder 175), so as to        produce 26-bit sums (outputs 173 and 178 respectively),    -   two 26-bit registers 174 and 179 respectively at the outputs 173        and 178 of the adders 170 and 175 (outputs to OUT_CALC12 and        OUT_CALC34 lines),    -   one 26-bit adder 180 having inputs 181 and 182 respectively        linked to the registers 174 and 179, producing at the output 183        the sum OUT1234 of the calculation results from the four modules        130, 140, 150 and 160,    -   one multiplexer 195 for selecting a cascade input (IN_CASCAD        line) originating from an upstream network (input 196), or from        the earth (input 197), having an output 198,    -   one assembly 184 of four 26-bit registers at the output 183 of        the adder 180, for the resetting of OUT1234 on the cascade        input,    -   one multiplexer 185 giving at the output 188 the sum OUT1234,        either by direct connection to the output 183 of the adder 180        (input 186) or by way of the assembly 184 of registers (delay        for cascade input, input 187),    -   one 30-bit adder 190 making it possible to cascade the networks        of filters, having a first input 191 linked to the output 198 of        the multiplexer 195, a second input 192 linked to the output 188        of the multiplexer 185 and an output 193 and    -   one 30-bit register at the output 193 of the cascade adder 190        (output to an OUT_CASCAD line).

The new configuration parameters required are those relating to themultiplexers 141, 151 and 161 (video input selections) and to themultiplexer 195 (consideration of an upstream network).

The formatting and the multiplexing of the signals is performed in sucha way as to obtain a splitting of the inputs/outputs representing acompromise between flexibility of access to the data and number ofinputs/outputs. The latter number is in general a heavy constraint, inparticular in the case of a VLSI implementation.

In general, the number and the arrangement of the multiplexers areoptimized in such a way as to access various filter combinationsprovided for by the structure.

In the embodiment disclosed, the network 120 supplemented withformatting and multiplexing information (as illustrated in FIG. 4)comprises as inputs the following lines:

-   -   IN_CASCAD: 30-bit cascade input making it possible to associate        several networks,    -   IN_VIDEO 1 . . . 4: four video trains, making it possible to        access the modules 130, 140, 150 and 160 respectively,    -   ADR_COEFF1 . . . 2: addressing of the coefficients preloaded in        the banks, with dynamic switching (at the pixel rate), each line        being common to two modules (respectively modules 130 and 140 on        the one hand, and 150 and 160 on the other hand),    -   WE_POINT1 . . . 2 and WE_LINE1 . . . 2: disabling of the        pointwise and linewise shifting, common to two modules        (respectively modules 130 and 140 on the one hand, and 150 and        160 on the other hand),    -   IN_VECTX and IN_VECTY: vector inputs for the random access        application,    -   IN_DOWNLOADING: downloading bus for the configuration including        the positioning of the multiplexers and the coefficients of the        sixteen cells.

Moreover, the network 120 comprises at output (FIG. 4) four buses OUT1 .. . OUT4 each of 10 bits. The latter correspond to a multiplexing and toa formatting whose configuration depends on the requirements of theapplication. Thus, in all the configurations, there cannot be more than40 output bits. The four buses OUT1 . . . OUT4 are linked to the outputsOUT_VIDEO1 . . . OUT_VIDEO4, OUT_CALC1 . . . OUT_CALC4, OUT_CALC 12,OUT_CALC34 and OUT_CASCAD by multiplexers 200 (inputs OUT_VIDEO1 andOUT_VIDEO2), 201 (inputs OUT_CALC2 and OUT_CALC12), 202 (inputsOUT_CALC3 and OUT_CALC34, 203 (inputs OUT_VIDEO3 and OUT_VIDEO4), 204(inputs: output of the multiplexer 200 and OUT_CALC1), 205 (inputs:outputs of the multiplexers 202 and 203), 206 (inputs: outputs of themultiplexers 201 and 204), 207 (inputs: output of the multiplexer 205and OUT_CALC4), 208 (inputs: output of the multiplexer 206 andOUT_CASCAD), 209 (inputs: output of the multiplexer 201 and OUT_CASCAD)and 210 (inputs OUT_CALC4 and OUT_CASCAD). Moreover, shifting androunding units 211-215 respectively followed by registers 216–220 arerespectively interposed between the calculation outputs (OUT_CALC1,output of the multiplexer 201, OUT_CASCAD, OUT_CALC4, output of themultiplexer 202) and the corresponding inputs of the multiplexers204–210.

In the examples of use hereinbelow, to each filter configuration therecorresponds a programming dedicated to formatting and to multiplexing.For example, for a cascaded use, the output delivers the 30-bit signalOUT_CASCAD accompanied by a delayed 10-bit source video signal(OUT_VIDEO3 or 4), these two signals joined leading to a 40-bit word.

For the use of the network 120 as a temporal filter, frame memoriesorganized as a FIFO are employed in the construction of the filter.According to an advantageous embodiment, these memories are integratedinto the overall architecture. In another advantageous embodiment, theyare regarded as external items inserted only as required.

The following examples of filters (Examples 1 to 3) are obtained on thebasis of the network 120, configured and parameterized in particularways by downloading.

EXAMPLE 1 Symmetric Horizontal-vertical Filter

The properties of such a filter, represented in FIG. 5 and referenced120A, are as follows:

-   -   one input (IN_VIDEO1),    -   one output (OUT_VIDEO4),    -   5*5 coefficients with odd symmetry        -   (C12,C13,C14,C13,C12,            -   C9,C10,C11,C10,C9,            -   C6,C7,C8,C7,C6            -   C3,C4,C5,C4,C3            -   C0,C1,C2,C1,C0)    -   sum of the coefficients 1024,    -   800 points by 600 lines,    -   active rounding and clipping.

The horizontal symmetries are taken into account by virtue of the delaysapplied to the LARs 5 of the cells 1 of the four modules 130, 140, 150and 160 of the network 120 (a delay of n points in a LAR is indicated inFIG. 5 by the notation “n pts” in the LAR).

For each cell 1 used to exploit a horizontal symmetry, the adder 7receives at the inputs 21 and 22 respectively the input and the outputof the LAR 5, the latter producing a delay equal to the horizontaloffset between two points having the same coefficients. For example, thefirst cell 1 of the module 130 has its LAR 5 which imposes a delay offour points and its bank 9 of coefficients which is associated with thecoefficient C0. Moreover, the circulation output 3 receives the outputfrom the register 16 (shifting of one point).

For each of the line jump cells 1 (coefficients C2, C5, C8, C11 andC14), the adder 7 receives at the input 21 the input 2 from the cell 1and nothing at the input 22. The circulation output 3 for its partreceives the output from the LAR 5, the latter producing a delay ofpositioning on the next line. For example, the third cell of the module130 has its LAR 5 which imposes a delay of 798 points and its bank 9 ofcoefficients which is associated with the coefficient C2. As far as thelast cell 1 is concerned (fourth cell of the module 160), its additionfunctions are deactivated, the inputs 21 and 22 of the adder 7 being setto zero.

EXAMPLE 2 Temporal Vertical Filter

The properties of such a filter, represented in FIG. 6 and referenced120B, are as follows:

-   -   four inputs IN_VIDEO1. . . IN_VIDEO4,    -   one output OUT_CASCAD,    -   4*4 coefficients (without particular symmetry)        -   (C0,C1,C2,C3,            -   C4,C5,C6,C7,            -   C8,C9,C10,C11,            -   C12,C13,C14,C15)    -   sum of the coefficients 1024,    -   800 points by 600 lines,    -   active rounding and clipping.

The adders of all the cells 1 receive at the inputs 22 the outputs fromthe LARs 5 and nothing at the inputs 21, the LARs 5 imposing delays of800 points. Moreover, the circulation outputs 3 likewise receive theoutputs from the LARs 5.

EXAMPLE 3 Horizontal Filter with Odd Symmetry

The properties of such a filter, represented in FIG. 7 and referenced120C, are as follows:

-   -   one input IN_VIDEO1,    -   one output OUT_CASCAD,    -   31 coefficients with odd symmetry (C0,C1 . . . ,C15, . . .        C1,C0),    -   sum of the coefficients 1024,    -   800 points by 600 lines,    -   active rounding and clipping.

All the cells 1 are carriers of horizontal symmetries, except for thecell 1 associated with the central point (coefficient C15). Apart fromthe latter cell, the cells 1 therefore have their adders respectivelyreceiving at the inputs 21 and at the outputs 22 the inputs and theoutputs of the LARs 5, and their circulation outputs 3 receiving theoutputs from the registers 16. These LARs 5 impose delays, the greatestof which is equal to 30 for the upstream cell 1 (of the module 130), anddecreasing by two points on going from each cell to the next cell 1,down to the value of two points. The last cell 1 (of the module 160),associated with the coefficient C15, is not associated with anysymmetry. Its adder 7 receives at the input 21 the input 2 from the cell1 and nothing at the input 22, and its circulation output 3 receives theoutput from the register 16.

In other embodiments of the network, the LAR 5 is capable of producingdelays of several lines. The network thus obtained can serve to takeinto account vertical symmetries, with a vertical amplitude ofprocessing of the symmetries corresponding to the number of lines ofthis LAR. The latter is therefore advantageously capable of generating adelay (at least) equal to the total number of lines of the image. In avariant embodiment, the capacity of the LAR is less than the totalnumber of lines of an image, and is adapted to the maximum height of thefilters used in practice in the intended applications.

Preferably, in the embodiments in which the LAR 5 is capable ofproducing delays of several lines, the register 16 is replaced with adelay line, advantageously having a capacity of at least one line. Theperformance of the filter in respect of going from one line to anothermay thus be improved.

EXAMPLE 4 Image Format Expansion Filter

Such a filter 230, represented in FIG. 8, implements the disablingfunctions on the basis of an architecture based on modules M1–M4identical to that 60 of FIG. 2, arranged as a network 120D.

The filter 230 comprises:

-   -   the four modules M1 to M4 each of four coefficients, the modules        M1 and M2 being intended for horizontal interpolation and the        modules M3 and M4 for vertical interpolation;    -   a head memory 231 for rate conversion, arranged upstream of the        modules M1–M4,    -   two clock inputs H_SOURCE and H_OUTPUT in the head memory 231,        which are designed to give respectively the rates of the source        image and of the output image,    -   point disabling lines WE_POINT linked to the modules M1 and M2        and line disabling lines WE_LINE linked to the modules M3 and        M4.

The output OUTVIDEO2 of the module M2, corresponding to the horizontalinterpolation, is connected to the input INVIDEO3 of the module M3,which leads to a vertical interpolation.

The separation of the point and line disabling signals per group of twomodules makes it possible to carry out in one and the same element ahorizontal expansion and a vertical expansion in a single processingpass. The head memory 231 makes it possible to generate a change ofpixel rate or pixel clock, which corresponds to that resulting from achange of image format. Writing to this memory 231 is carried out at therate of the source image (given by H_SOURCE), whilst reading from thismemory is carried out at the rate of the output image (given byH_OUTPUT). In this way, only the pixels which are useful for thefiltering operation are stored.

In a particular implementation, a zoom centred on the middle of theimage is performed. The expansion factor in each direction is 2 and theinterpolator filter 230 uses eight coefficients in each direction.

For the horizontal interpolation, effected in the modules M1 and M2, apoint disabling is performed every pixel entering the filter 230 orevery two pixels exiting the filter 230. Reading of the head memory 231and also pixel shifting in the filter 230 are then frozen by the signalWE_POINT. Twice as many pixels are thus obtained at the output of themodules M1 and M2 as at the input.

For the vertical interpolation, the procedure is similar, but with afreezing by the signal WE_LINE of the line shifting, for each newincoming line or every second line exiting the modules M3 and M4. Thevertical-wise rate conversion is also carried out by the head memory231, this involving the repeating of the horizontal interpolation foreach line disabled. The line disabling is in fact performed in the headmemory 231 on the pixels of the source image.

In a particular application of image format conversion, the conversionis from a TV signal to a HD TV signal. The TV image is then stored inthe head memory 231 at the TV clock rate and it is read back at the HDTV rate to carry out horizontal and vertical expansions.

EXAMPLE 5 Undersampling (Compression) Filter

Such a compression filter 240, represented in FIG. 9, is also obtainedthrough an architecture based on modules M1–M4 identical to that 60 ofFIG. 2, but comprises an output memory 241 having a rate conversionfunction.

This memory 241 is furnished with a point and line disabling inputWE_PT_LG, which allows a selection of the useful points and lines. Italso comprises the clock inputs H_SOURCE and H_OUTPUT, respectivelygiving the rates of writing (information originating from the modules)and of reading (reduced output image) for this memory 241.

The functions of the modules M1 to M4 are similar to those set forth inExample 4 in respect of expansion.

This undersampling filter 240 makes it possible to reduce the size ofthe image in terms of number of points and lines, this operation beingaccompanied by filtering which makes it possible to comply withShannon's law.

The filter 240 operates at the rate of the source image and it carriesout more interpolations than necessary, since it provides a pixel at itsoutput for each input pixel and a line for each input line. The outputmemory 241 performs selection of the useful points and lines (inputsignal WE_(—PT)_LG) and is subsequently read at the rate of the reducedoutput image.

The ensuing part of the description is devoted to the random accessfunctions, which may be implemented instead of a linear filtering on thebasis of elements similar to those set forth earlier, by virtue ofstraightforward adaptations.

A particularly beneficial application of random access is motioncompensation. In a corresponding operation of pixel access, illustratedin FIG. 10, the current address is carried by a frame T undergoinginterpolation, situated between two frames, preceding T1 and followingT2 (bidirectional random access). The interpolation of a point M of thecurrent frame T calls upon the pixels of the two adjacent frames T1 andT2, which are situated in the immediate vicinity of the points of impactof an interpolation vector V. The point M is calculated by weighting thevalues of the two points of impact as a function of a coefficient α(lying between 0 for T placed in T1 and 1 for T placed in T2) giving therelative position of the frame T with respect to T1 and T2. The pointsof impact are themselves calculated by interpolation from the pixels oftheir environments. In the examples set forth, a bilinear interpolationis performed using only the four pixels A1, B1, C1 and D1 for T1 and A2,B2, C2 and D2 for T2 respectively flanking each of the points of impactM1 and M2. Moreover, an accuracy of interpolation of as much as aquarter of a pixel is defined, using an accuracy of the addresses ofimpact to a quarter of a pixel. This leads to the distinguishing of afractional part of these addresses, which is represented by a fractionalpart of two bits. This fractional part determines the coefficients ofthe interpolation carried out on the basis of the four pixels flankingthe impact of the vector V, respectively in the frames T1 and T2.

The succession of operations performed is as follows:

-   -   Calculation of the addresses of impact A1 and A2 respectively in        the frames T1 and T2 as a function of a vector V referenced from        T2 to T1:        V1(x,y)=α*V(x,y)        V2(x,y)=(1−α)*V(x,y);        the quadruples are then tagged by the addresses of the pixels A1        and A2:        A1(x,y)=M(x,y)+Ent[V1(x,y)]        A2(x,y)=M(x,y)+Ent[V2(x,y)]        where Ent corresponds to the extraction of the integer part;    -   Interpolation of the points of impact M1 and M2        M1=A1*(1−Fr[V1(x)])*(1−Fr[V1(y)])+B1*Fr[V1(x)]*(1−Fr[V1(y)])+C1*(1−Fr[V1(x)])*Fr[V1(y)]+D1*Fr[V1(x)]*Fr[V1(y)]        M2=A2*(1−Fr[V1(x)])*(1−Fr[V1(y)])+B2*Fr[V1(x)]*(1−Fr[V1(y)])+C2*(1−Fr[V1(x)])*Fr[V1(y)]+D2*Fr[V1(x)]*Fr[V1(y)]        where Fr represents the extraction of the fractional part of a        component of the vector;    -   Interpolation of the point M:        M=(1−α)*M1+α*M2.

An element, represented in FIGS. 11 to 13, used for these operationsrelies on the use of four modules 250 similar to that 60 of FIG. 2. Themodules 250 (FIG. 11) each comprise four cells 261, 271, 281 and 291 andare modified as follows:

-   -   separation of each line memory (delay lines 265, 275, 285 and        295 respectively of the cells 261, 271, 281 and 291) of 2048        pixels into two RAM memories 301 and 302 of 1024 pixels each (a        delay RAM a line 4 at 1028) leading to a total of 32 lines,    -   association of 64-word access RAMs 256–259 (64×40 dual port        RAMs) respectively with the delay lines 265, 275, 285 and 295 of        the cells 261, 271, 281 and 291.

These supplements make it possible to yield a RAM depth equal to themaximum excursion of the vector in terms of X and Y, which is requiredfor the introduction of the random function. These maximum excursions ofthe vector are generally fixed at ±31 points and ±15 lines for mostsystems with motion compensation. They therefore necessitate theavailability of a memory space with a depth of 64 points on 32 lines.

These access RAMS 256–259, of smaller capacity than the delay lines 265,275, 285 and 295 and arranged in parallel with these lines, make itpossible to remedy the access time limitation problems which would arisethrough the exclusive use of the RAMs of the delay lines 265, 275, 285and 295. They are used only for random access. To support the maximum Xsize of the vector, 64-point RAMs are required. However, recourse isadvantageously had to a duplication of the access RAM, since it is thuspossible to access two consecutive points of the same line in a clockcycle, these points being written at the same address. Hence, accessRAMs of 64*20 words per line are used. The basic cells 261, 271, 281 and291 possess two lines of 1024 pixels, and it is necessary to associatetwo RAMs of 64*20 therewith, which can be manifested by a 64*40 RAM.

The module 250 is therefore enhanced with the RAMs 256–259 of 64 wordsof 40 bits and with new multiplexers dedicated to the random accessfunction (FIG. 11):

-   -   MUXA and MUXB, which each have two outputs respectively        connected to the access RAMs 256 and 257,    -   MUXC and MUXD, which each have two outputs respectively        connected to the access RAMs 258 and 259,    -   MUXE, which has two outputs respectively connected to the inputs        of the multiplexers MUXA and MUXC,    -   MUXF, which has two outputs respectively connected to the inputs        of the multiplexers MUXB and MUXD,    -   MUXG, which has an output connected to the input of MUXE and        another at zero,    -   and MUXH, which has an output connected to the input of MUXF and        another at zero.

Writing to the access RAM 256–259 is done in pipeline mode at the clockfrequency of the input video. With each write, the value written 64clock ticks earlier is overwritten. At readout level, to obtain a squaregrid as required, we calculate the address pointed at by the vectorwhich serves to select the pair of pixels along the X axis and the pairof lines along the Y axis.

In another embodiment for random access, the pixels acquisition functionforms an integral part of the LARs delay memories 265, 275, 285 and 295.The latter permit in this case read/write times which are sufficientlysmall as to allow the total number of read/write accesses required bothfor the delay function and for the random access function. The overallprinciple does not change, the outputs of the LARs 265, 275, 285 and 295being redirected respectively to the multiplexers MUX5, which gather therandom access data.

The modules 250 are advantageously devised in such a way as to carry outtwo types of access:

-   -   bidirectional access, as illustrated by FIG. 10, in which two        modules 250 are assigned to each frame T1 and T2; these two        modules then make up a block: BLOC1 for frame T1 and BLOC2 for        frame T2; the vertical excursion of the vector is in this case        limited to ±7 lines; according to an advantageous embodiment,        this excursion is extended by cascading several networks;    -   monodirectional access, which consists in accessing a single        frame to which all the lines are allotted; the vertical        excursion of the vector is then a maximum and equal to ±15 lines        for a single network.

The network is therefore still structured as modules as in the case offiltering, each module 250 taking on board either the whole of thebilinear interpolation when the quadruple of pixels emanates entirelyfrom its RAMs, or half of the interpolation when only half of the pixelsoriginate from its RAMs.

The interpolation with random access ultimately comprises two steps: theselecting of the quadruple of pixels and bilinear interpolation.

The first step, selecting of the quadruple, is performed by virtue of anassembly for generation of addresses 310 of the relevant network 320(FIG. 12). This assembly 310 comprises:

-   -   a timebase unit 311, receiving a FIELD_SYNC synchronization        signal and producing information on a current point,    -   a write unit 312 modulo 64, receiving the information regarding        current point of the timebase unit 311 and writing write data        modulo 64 to the RAMs of the cells,    -   a calculation unit 313, receiving the components Vx and Vy of        the vector V and the coefficient α respectively via the lines        IN_VECX, IN_VECY and ALPHA and generating products of the        components Vx and Vy times the factors α or (α−1),    -   an adder 314 modulo 64, receiving the information regarding        current point of the timebase unit 311 and the products α.Vx and        (α−1).Vx from the calculation unit 313, and generating        addressing data for the RAMs contained in the blocks BLOC1 and        BLOC2 respectively via two lines RAM_BLOC1 and RAM_BLOC2,    -   an integer part decoding unit 315, receiving the products α.Vy        and (α−1).Vy from the calculation unit 313, and generating        addressing data for the multiplexers MUXA to MUXH of the four        modules of the network, respectively via four lines        MODULE1–MODULE4, and    -   a fractional part decoding unit 316, receiving the products        α.Vx, α.Vy, (α−1).Vx and (α−1).Vy from the calculation unit 313,        and generating coefficients intended for the banks 9 of the        blocks BLOC1 and BLOC2, respectively via two lines COEFF_BLOC1        and COEFF_BLOC2.

The step of selection of the quadruple entails:

-   -   a selection along the X axis, which is performed by addressing        the 64-word access RAMs 256–259 (via the adder 314); for this        addressing, all the modules 250 and the cells assigned to one        and the same frame are addressed identically; and    -   a selection along the Y axis, which is performed with the aid of        the multiplexers MUXA to MUXH of each module 250 (via the        integer part decoding unit 315); if the lines stored in one of        the modules 250 does not contain any pixel of the quadruple,        then the multiplexers MUXG and MUXH direct a zero value to the        multipliers 8; if they contain only two pixels of the quadruple,        then just one of the two multiplexers MUXG and MUXH is        validated; this signifies that the states of the multiplexers        MUXA to MUXF may be common to all the modules 250, whilst those        of the multiplexers MUXG and MUXH must be dedicated to the        modules 250.

The second step, the bilinear interpolation, is carried out by means ofthe multipliers 8 associated with the banks 9 of coefficients. Thecoefficient addressed to each multiplier 8 (by the fractional partdecoding unit 316) corresponds to the contribution which the pixelshould have in the bilinear interpolation operation. The addressing ofthe bank 9 of coefficients is therefore calculated on the basis of thefractional parts of the addresses of impact in T1 and T2, as well as thecontributions α and (0α−1).

The network formed from the modules 250 corresponds for example to thenetwork 120 (FIGS. 3 and 4) used in linear filtering.

The configuration described hereinabove applies to the most common casesof using the architecture in random access mode, which calls uponbilinear interpolation.

A particular network embodiment, referenced 320 and represented in FIG.13, applies also to less usual cases, which require more sophisticatedinterpolations and manipulations of pixels, which cannot be anticipatedand provided for in a basic version of the architecture describedearlier. This embodiment makes it possible for the four pixels flankingthe point of impact to be output simply without further processing. Thismanner of operation applies to single-frame access employing 32 linesvertically, the four pixels then being delivered respectively on thefour outputs OUT1 . . . OUT4.

The network embodiment 320 makes it possible to preserve in tact thearchitecture described earlier (based on that of the network 120 used inlinear filtering), while supplementing it by means of an assembly 321 ofadditional items for pixel access. The assembly 321 comprisesmultiplexers arranged in parallel with this architecture, permitting theimplementation of this functionality. To aid the reading of FIG. 13, theseries of multiplexers 204 to 210 of the network 320 is brought togetherin an output block 330. The assembly 321 comprises three levels ofmultiplexing:

-   -   a first multiplexing level comprising four OR gates 335–338 each        having four inputs, respectively receiving truncated calculation        outputs OUT_C1 . . . 16 consisting of the 10 least significant        bits of the calculation outputs 4 from the sixteen cells of the        network 320; the four inputs of each of the OR gates 335–338        respectively receive one of the truncated outputs OUT_C1 . . .        16 from the four modules 250 of the network 320, the OR gates        335–338 respectively receiving the outputs from the first (261),        the second (271), the third (281) and the fourth (291) cells of        each of the four modules 250,    -   a second multiplexing level comprising four multiplexers 331–334        for reordering the pixels in a desired order, controlled by a        command 322 determined by the least significant bit of the        integer part of the component Y of the address of the point of        impact M1 or M2, these multiplexers 331–334 having as respective        inputs the outputs of the gates 335 and 337, 336 and 338, 335        and 337, and 336 and 338,    -   a third multiplexing level comprising four multiplexers 341–344        for output selection, controlled by an output selection command        323, each having as first input an output of the output block        330 corresponding to an interpolated output mode, having as        second inputs respectively the outputs of the multiplexers 334,        333, 332 and 331, corresponding to a four pixel output mode, and        having as outputs respectively output lines OUT1–OUT4 on 10 bits        each.

In the mode of operation for extracting the pixels flanking the point ofimpact (four pixel output mode), the basic cells 261, 271, 281, 291 . .. operate in a similar manner to the interpolated output mode, but themultipliers 8 are positioned transparently by the selecting of acoefficient equal to unity in all the banks 9 of coefficients. The ORgates 335–338 then direct via the OR logic function the appropriateoutputs from the cells to the four outputs OUT1 . . . OUT4 of theoverall network 320. The reordering is for its part performed by themultiplexers 331–334 according to the parity of the Y component of theaddress of impact.

Examples of application of random access are given hereinbelow (withreference to FIGS. 14 to 16). They are obtained on the basis ofparticular configurations of the network 320, whose four modules arereferenced 251–254 respectively, and whose addressing multiplexersMUXA-MUXH are represented in the form of multiplexing bars, referenced351–354 respectively for the modules 251–254. FIGS. 14 and 15 show thevarious paths taken by the data in interpolated output mode and FIG. 16those taken in four pixel output mode. In all cases presented, the firstinputs 21 of the adders 7 are connected to the outputs of themultiplexers MUXG (first and second cells) and MUXH (third and fourthcells) of the modules 250 to which they respectively belong, via themultiplexers MUX5 of their cells 1, and their second inputs 22 are setto zero.

The grid considered comprises four points A, B, C and D, distributed inthe following manner:

A B C D

Indicated in FIGS. 14 to 16 are the pixels obtained respectively at theoutputs of the cells of the first module 351. The letter on the leftcorresponds to an even value of the Y component of the address and thaton the right to an odd value. The output pixels from the four cells ofthe module 351 are thus respectively D, C, B and A for Y even, and B, A,D and C for Y odd. The reordering, vertical only, is performed ininterpolated output mode by appropriate selection of the coefficients inthe bank 9, and in four pixel output mode, by the multiplexers 331–334.

The interpolated output mode can be programmed according to two forms ofimplementation: a first form with a single video input and a vectorwhich can range from + or − 15 lines, and a second form with two videoinputs and a vector with excursion of + or − 7 lines. These twosituations are respectively illustrated in Examples 6 and 7 hereinbelow.

EXAMPLE 6 Random Access on 32 Lines

The network configuration 320 of the present example referenced 320A andrepresented in FIG. 14, involves a single video input IN_VIDEO1 and acalculation output OUT_CASCAD. The coefficients C0, C1, C2 and C3 arecommon to the four modules 251–254.

An analysis is performed on the two terms α.Vx and α.Vy. The address ofthe coefficients C0, C1, C2 and C3 is dependent on the fractional partof the values α.Vx and α.Vy and the positionings of the multiplexersMUXA–MUXH depend on the integer part of the value α.Vy. For a value ofα.Vy=−12.5, for example, lines −13 and −12 are accessed.

EXAMPLE 7 Dual Random Access on 16 Lines

In this example, the network configuration 320, referenced 320B andrepresented in FIG. 15, relies on the use of two video inputs IN_VIDEO1(input of the module 251) and IN_VIDEO3 (input of the module 253) and ofthe calculation output OUT_CASCAD. The terms α.Vy, α.Vx, (α−1).Vx and(α−1).Vy are calculated at the level of the element (such as an ASIC).Specifically, when two accesses are requested, they are both dependenton the same vector but in opposite directions. An analysis is thusperformed on the four terms above, this requiring dual decoding.Example:α=0.3, Vx=25, Vy=−5α.Vy=−1.5, α.Vx=7.5, (α−1).Vx=−17.5 and (α−1).Vy=3.5.

At the level of the coefficients of the multipliers 8, two cases arepossible according to the application. In a first form ofimplementation, two bilinear interpolations are carried out and the tworesults are kept. In this case, the banks 9 of coefficients C0–C3 andC4–C7 are downloaded with the same values. In a second form ofimplementation, a temporal interpolation is carried out between the twobilinear interpolations. To do this, a correction term is applied to thecoefficients C0–C7 according to the phase to be calculated.

EXAMPLE 8 Random Access with 4 Pixels without Interpolation

In such an embodiment, the network configuration 320, referenced 320Cand represented in FIG. 16, makes it possible to retrieve at output thefour points of the 2*2 grid pointed at by the vector. The elementcomprises 40 output pins, which make this extraction of informationpossible. During operation, a coefficient equal to 1 is applied in allthe banks 9 of coefficients and the points A, B, C and D are routed atoutput by means of the truncated outputs OUT_C1-OUT_C16 respectivelyarranged on the ten least significant bits of the calculation outputs 4,to the OR gates 335–338 of the assembly 321. The reordering of therelevant grid is managed as a function of the parity of the Y componentof the address of the point of impact, by means of the multiplexers331–334.

1. Elementary cell of a linear filter for image processing, comprising:an input, intended to sequentially receive data relating to pixels of animage to be processed, a circulation output, intended to sequentiallytransmit the said data with a delay, a calculation output intended tosequentially transmit results obtained by a processing of the said datain said elementary cell, a main delay line having an input capable ofbeing linked to the input of said elementary cell and an output capableof being linked to the circulation output and to the calculation outputof said elementary cell, a coefficients memory, provided so as tocontain at least one multiplier coefficient, and a multiplier connectedto the coefficients memory, having an input and an output which arecapable of being linked respectively to the output of the main delayline and to the calculation output of said elementary cell, the saidmultiplier being intended to perform multiplications on the said datareceived at the input of the said multiplier by at least one of the saidmultiplier coefficients of the coefficients memory and to transmit viathe output of the said multiplier the result obtained, wherein the maindelay line is capable of producing a maximum shift corresponding to atleast two pixels of the image to be processed and in that saidelementary cell also comprises: an auxiliary delay line having an inputand an output which are capable of being linked respectively to theinput of said elementary cell and to the circulation output of saidelementary cell, an adder having a first and a second input which arecapable of being linked respectively to the input of said elementarycell and to the output of the main delay line, and an output capable ofbeing linked to the multiplier, delay line selection means having afirst and a second state, the said means being intended to link theinput of said elementary cell to the circulation output of saidelementary cell by way of the main delay line in the first state and byway of the auxiliary delay line in the second state, and calculationselection means having at least two states, the said means beingintended to link the input of said elementary cell and/or the output ofthe said main delay line to the corresponding inputs of the adder, inthe said states respectively.
 2. An elementary cell according to claim1, wherein the main and auxiliary delay lines are respectively capableof producing maximum shifts of at least one line and one point, theauxiliary delay line preferably comprising a register.
 3. An elementarycell according to claim 1, wherein the main and auxiliary delay linesare respectively capable of producing maximum shifts of at least twolines and at least one line.
 4. An elementary cell according to claim 1,wherein the coefficients memory consists of a memory intended forstoring a bank of coefficients and in that said elementary cellcomprises means for selecting one of the said coefficients.
 5. Anelementary cell according to claim 1, wherein the said elementary cellcomprises shift disabling means for at least one of the said delaylines.
 6. An elementary cell according to claim 1, wherein the saidcalculation selection means comprise: a first multiplexer having a firstinput linked to the input of said elementary cell, a second input linkedto the zero and an output linked to the first input of the addercorresponding to the input of said elementary cell, and a secondmultiplexer having a first input linked to the output of the main delayline, a second input linked to the zero and an output linked to thesecond input of the adder corresponding to the output of the main delayline.
 7. An elementary cell according to claim 1, wherein saidelementary cell comprises at least one control line intended fordownloading control information to at least one item of said elementarycell, the said control lines being chosen from: at least one line foraddressing multiplier coefficients intended for the said coefficientsmemory, at least one line for addressing parameters for selectingcoefficients, intended for the said coefficients memory, the saidparameters preferably consisting of address bits, at least one line foraddressing data for activating and for deactivating the said shiftdisabling means, the said data preferably comprising information on thelinewise and pointwise shift disabling, at least one line for addressingdelay selection parameters, intended for at least one of the said delaylines, at least one line for addressing state selection parameters,intended for the delay line selection means and/or calculation selectionmeans, and any combination of the said addressing lines.
 8. A linearfilter for image processing, comprising at least three elementary cellsin accordance with claim 1, said elementary cells being arranged incascade to form a module consisting of an input elementary cell anintermediate elementary cell and an output elementary cell, the saidmodule also comprising addition means linked to the calculation outputsof said elementary cells and having an input linked to the input of saidinput elementary cell, a circulation output linked to the circulationoutput of said output elementary cell and a calculation outputdownstream of the addition means.
 9. A module for a linear filter forimage processing according to claim 8, wherein said module furthercomprises random access selection means, in particular for motioncompensation, having a first and a second state, the said random accessselection means being intended to connect the input of each of saidelementary cells to the first input of the adder of said cell in thefirst state, and the output of at least one of the said delay lines ofeach of said cells to the first input of the adder of one of said cellsin the second state.
 10. Linear filter for image processing, comprisingat least two modules in accordance with claim 8, the said linear filteralso comprising addition means linked to said calculation outputs of atleast two of the said modules.
 11. Linear filter according to claim 10,wherein the said modules are arranged in cascade and in that the saidlinear filter also comprises input selection means having a first and asecond state, arranged between at least one of the said modules, theso-called upstream module, and the consecutive module, the so-calleddownstream module, the said input selection means being intended to linkthe input of the downstream module to the circulation output of theupstream module in the first state, and to an additional input line inthe second state.
 12. Linear filtering process for image processingcomprising: sequentially sending data relating to pixels of an image tobe processed to inputs of elementary cells in cascade, whilerespectively imposing, in said elementary cells, transmission delays forthe said data, performing multiplications by multiplier coefficients inat least one part of said elementary cells on the data received by saidelementary cells, so as to obtain products, and adding the said productstogether, wherein in at least one of said elementary cells: a main delayand an auxiliary delay less than the said main delay are imposed on thedata received by said one elementary cell, by means of two delay lines,respectively main and auxiliary, in parallel, the data received by thesaid one elementary cell are added together, upstream and downstream ofthe main delay line so as to obtain sums and the said multiplicationsare performed on the said sums, and the data received by the said oneelementary cell are transmitted downstream of said one elementary cell,with the said auxiliary delay.